Conventionally, a thin film of pure aluminum or its alloy has been used as a material to interconnect wires in semiconductor devices. The aluminum interconnect provides high conductivity, a simple process for generating patterns, strong adhesion with a silicon insulating layer and a low cost method for fabricating an interconnect in semiconductor devices. However, in pursuit of high integration in fabricating integrated circuits, the area of a unit cell of a semiconductor device has gradually been reduced. As a result, the area on which an interconnect is made is also decreased. This reduction in area results in the diminution of the operation speed of the device. A copper interconnect is, therefore, used to improve and maintain the operation speed in the semiconductor device. Because the copper interconnect cannot be directly etched at present, a damascene process and a CMP process are sequentially performed to fabricate the copper interconnect.
However, during the etching process of a nitride layer to form a contact hole and to connect an upper copper interconnect with a bottom copper connection, the bottom copper interconnect may be etched together with the nitride layer. The etching of the bottom copper interconnect may cause sputtering and generate copper ions and nitride polymers. The copper ions and nitride polymers may contaminate the surface of the substrate.
According to the conventional method, polymers from the silicon nitride layer of a capping layer are removed by an HF solvent. However, the copper contaminants are not completely removed by this process, but instead remain on the substrate and eventually affect the operation of the semiconductor device. High integration in semiconductor devices thus necessitates a transition of the material to insulate a copper interconnect from SiO2 to a low dielectric material such as SiOC, and this requires new cleaning methods and apparatus.
Bergman, U.S. Pat. No. 5,954,911, describes a method and an apparatus using a vapor phase process stream made from a liquid phase source and feed gas.
Fayfield et al., U.S. Pat. No. 6,065,481, describes a method and an apparatus for direct delivery of an enabling chemical gas from a liquid source and of HF gas in a HF/enabling chemical based cleaning or etching process such as a silicon dioxide film etching process. The liquid enabling chemical is temperature controlled to generate a vapor pressure which is sufficient to operate a mass flow controller at a desired processing pressure without a carrier gas.
Fayfield et al., U.S. Pat. No. 6,299,724, describes an apparatus and method for direct delivery of an enabling chemical gas from a liquid source and of HF gas in a HF/enabling chemical based cleaning or etching process such as a silicon dioxide film etching process. The liquid enabling chemical is temperature controlled to generate a vapor pressure which is sufficient to operate a mass flow controller at a desired processing pressure without a carrier gas. However, the method described in the '724 Patent requires a prolonged process time due to its complexity.
Silicon glass, (e.g., a kind of SiO2), is used as an insulating layer to form a conventional damascene structure. However, the conventional insulating layer in the copper interconnect has an RF delay problem due to the miniaturization of the copper interconnect. This delay problem is a main reason why a low dielectric material such as SiOC is substituted for SiO2 in order to form an insulating layer. These low dielectric materials, however, make it impossible to use the prior art cleaning methods in which organic solvents or diluted HF solution are used as a cleaning solution.